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preliminary 1 64 mb sdram ascend semiconductor corporation ascend semiconductor 64m sdram data sheet ascend semiconductor 64m sdram data sheet tel: (03)5635888 / fax: (03)5635188/ http://www .ascendsemi .com .tw
preliminary 2 64 mb sdram ascend semiconductor corporation ordering information ad 48 4m 16 4 4 v t a ? 7 l i ascend semiconductor edo : 40 fpm : 41 ddrsdram : 42 ddrsgram : 43 sgram : 46 sdram : 48 power non : standard l : low power density 16m : 16 mega bits 8m : 8 mega bits 4m : 4 mega bits 2m : 2 mega bits 1m : 1 mega bit refresh 1 : 1 k, 8 : 8k 2 : 2 k, 6 :16k 4 : 4 k bank 2 : 2 bank 6 : 16bank 4 : 4 bank 3 : 32bank 8 : 8 bank revision a : 1st b : 2nd c : 3rd d : 4th interface v : 3.3v r : 2.5v package min cycle time ( max freq.) - 55 : 5.5ns ( 183mhz ) - 6 : 6ns ( 167mhz ) - 7 : 7ns ( 143mhz ) - 8 : 8ns ( 125mhz ) - 10 : 10ns ( 100mhz ) - 15 : 15ns (66mhz,cl1 applicable) c: csp b: ubga t: tsop q: tqfp p: pqfp ( qfp ) organization 8 : x8 9 : x9 16 : x16 18 : x18 32 : x32 operating range i : industrial - 40 j ~ 85 j non : commercial 0 j ~ 70 j s : special 0 j ~ 85 j
preliminary 3 64 mb sdram ascend semiconductor corporation features ? fully synchronous to positive clock edge ? single 3.3v +/ - 0.3v power supply ? lvttl compatible with multiplexed address ? industrial temperature available ? programmable burst length ( bl ) - 1,2,4,8 or full page ? programmable cas latency ( cl ) - 1, 2 or 3 ? data mask ( dqm ) for read/write masking ? programmable wrap sequential - sequential ( bl = 1/2/4/8/full page ) - interleave ( bl = 1/2/4/8 ) ? burst read with single - bit write operation ? all inputs are sampled at the positive rising edge of the syste m clock. ? auto refresh and self refresh ? 4,096 refresh cycles / 64ms ordering information description the ad484m1644vta is synchronous dynamic random access memory ( sdram ) organized as 1,048,756 words x 4 banks x 16 bits. all inputs an d outputs are synchronized with the positive edge of the clock . the 64mb sdram uses synchr onized pipelined architecture to achieve high speed data transfer rates and is de signed to operate in 3.3v low power memory system. it also provides auto refresh with powe r saving / down mode. all inputs and outputs voltage levels are compatible with lvttl . 64 mb( 4banks ) synchronous dram ad484m1644vta ( 4mx16 ) * ascend semiconductor reserves the right to change products or sp ecification without notice. cl1 note low power low power low power standard standard standard standard power commercial range : 0 j ~ 70 j commercial range : 0 j ~ 70 j commercial range : 0 j ~ 70 j commercial range : 0 j ~ 70 j commercial range : 0 j ~ 70 j commercial range : 0 j ~ 70 j commercial range : 0 j ~ 70 j operation range 54 pins, tsopii 54 pins, tsopii 54 pins, tsopii 54 pins, tsopii 54 pins, tsopii 54 pins, tsopii 54 pins, tsopii package 100 mhz 125 mhz 143 mhz 66 mhz 143 mhz 167 mhz 183 mhz max freg . ad484m1644vta - 10l ad484m1644vta - 8l ad484m1644vta - 7l ad484m1644vta - 15 ad484m1644vta - 7 ad484m1644vta - 6 ad484m1644vta - 55 part number
preliminary 4 64 mb sdram ascend semiconductor corporation 54 pin tsop - ii (400milx875mil) (0.8mm pin pitch) pin assignment ( top view ) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 v dd dq0 v ddq dq1 dq2 v ssq dq3 dq4 v ddq dq5 dq6 v ssq dq7 v dd ldqm /we /cas /ras /cs ba0 ba1 a10/ap a0 a1 a2 a3 v dd v ss dq15 v ssq dq14 dq13 v ddq dq12 dq11 v ssq dq10 dq9 v ddq dq8 v ss nc udqm clk cke nc a11 a9 a8 a7 a6 a5 a4 v ss 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 ordering information * ascend semiconductor reserves the right to change products or sp ecification without notice. note low power low power low power standard standard standard power industrial range : - 40 j ~ 85 j industrial range : - 40 j ~ 85 j industrial range : - 40 j ~ 85 j industrial range : - 40 j ~ 85 j industrial range : - 40 j ~ 85 j industrial range : - 40 j ~ 85 j operation range 54 pins, tsopii 54 pins, tsopii 54 pins, tsopii 54 pins, tsopii 54 pins, tsopii 54 pins, tsopii package 100 mhz 125 mhz 143 mhz 100 mhz 125 mhz 143 mhz max freg . ad484m1644vta - 10li ad484m1644vta - 8li ad484m1644vta - 7li ad484m1644vta - 10i ad484m1644vta - 8i ad484m1644vta - 7i part number
preliminary 5 64 mb sdram ascend semiconductor corporation pin name pin function clk system clock master clock input(active on the positive rising edge) / cs chip select selects chip when active cke clock enable activates the clk when ? h ? and deactivates when ? l ? . cke should be enabled at least one cycle prior to new command. disable input buffers for power down in standby. a0 ~ a11 address row address (a0 to a11) is determined by a0 to a11 level at the bank active command cycle clk rising edge. ca(ca0 to ca7) is determined by a0 to a7 level at the read or write command cycle clk rising edge. and this column address becomes burst access start address. a10 defines the pre - charge mode. when a10 = high at the pre - charge command cycle, all banks are pre - charged. but when a10 = low at the pre - charge command cycle, only the bank that is selected by ba0/ba1 is pre - charged. / ras row address strobe latches row addresses on the positive rising edge of the clk with /ras ? l ? . enables row access & pre - charge. / cas column address strobe latches column addresses on the positive rising edge of the clk with /cas low. enables column access. / we write enable latches column addresses on the positive rising edge of the clk with /cas low. enables column access. ldqm/ udqm data input/output mask dqm controls i/o buffers. dq0 ~ 15 data input/output dq pins have the same function as i/o pins on a conventional dram. v dd /v ss power supply/ground v dd and v ss are power supply pins for internal circuits. pin descriptions ( simplified ) ba0, ba1 bank address selects which bank is to be active. nc no connection this pin is recommended to be left no connection on the device. v ddq /v ssq power supply/ground v ddq and v ssq are power supply pins for the output buffers.
preliminary 6 64 mb sdram ascend semiconductor corporation burst counter row add. buffer col. add. buffer col. decoder s/a & i/o gating block diagram a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 ba0 ba1 timing register cke /cs /ras /cas /we dqm row decoder memory array address register mode register set auto/self refresh counter col. add. counter write dqm control data in data out read dqm control dqi dqm dqm clk /clk
preliminary 7 64 mb sdram ascend semiconductor corporation idle row active active power down power down cbr refresh self refresh mode register set write writea read reada read suspend reada suspend write suspend writea suspend precharge power on simplified state diagram self self exit ref mrs cke cke act cke cke bst read read cke cke cke cke write read write with read with cke cke cke cke precharge pre pre write manual input automatic sequence
preliminary 8 64 mb sdram ascend semiconductor corporation ba1 ba0 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 operation mode cas latency bt burst length a2 a1 a0 sequential burst length interleave 0 0 0 1 1 0 0 1 2 2 0 1 0 4 4 0 1 1 8 8 1 0 0 reserved reserved 1 0 1 reserved reserved 1 1 0 reserved reserved 1 1 1 full page reserved a3 0 burst type sequential 1 interleave a6 a5 a4 cas latency 0 0 0 reserved 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 reserved 1 0 1 reserved 1 1 0 reserved 1 1 1 reserved ba1 ba0 a10 a9 a8 a7 0 0 0 0 0 0 0 0 0 1 0 0 operation mode normal burst read with single - bit write address input for mode register set a11 a11 0 0
preliminary 9 64 mb sdram ascend semiconductor corporation a2 a1 a0 interleave addressing burst length x x 0 0 1 2 x x 1 1 0 x 0 0 0 1 2 3 4 x 0 1 1 0 3 2 x 1 0 2 3 0 1 x 1 1 3 2 1 0 0 0 0 0 1 2 3 4 5 6 7 8 0 0 1 1 0 3 2 5 4 7 6 burst type ( a3 ) sequential addressing 0 1 1 0 0 1 2 3 1 2 3 0 2 3 0 1 3 0 1 2 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 0 0 1 0 2 3 0 1 6 7 4 5 0 1 1 3 2 1 0 7 6 5 4 1 0 0 4 5 6 7 0 1 2 3 1 0 1 5 4 7 6 1 0 3 2 1 1 0 6 7 4 5 2 3 0 1 1 1 1 7 6 5 4 3 2 1 0 n n n - 2 3 4 5 6 7 0 1 3 4 5 6 7 0 1 2 4 5 6 7 0 1 2 3 5 6 7 0 1 2 3 4 6 7 0 1 2 3 4 5 7 0 1 2 3 4 5 6 cn cn + 1 cn + 2 ? ... full page * * page length is a function of i/o organization and column address ing x32 (ca0 ~ ca7) : full page = 256 bits
preliminary 10 64 mb sdram ascend semiconductor corporation command symbol cke ignore command desl no operation nop truth table 1. command truth table ( ad484m1644vta ) h h x n - 1 n / cs h l x / ras x h / cas x h / we x h ba0, ba1 x x a10 x x a11, a9~a0 x x burst stop bsth read read h h x l l x h h h l l h x v x l x v read with auto pre - charge reada write writ h h x l l x h h l l h l v v h l v v write with auto pre - charge writa bank activate act h h x l l x l l h h h h v v h v v v pre - charge select bank pre h l x l h l v l x pre - charge all banks pall mode register set mrs h h x l l x l l h l l l x l h l x v note : h = high level, l = low level, x = high or low level (don't car e), v = valid data input command symbol cke data write / output enable enb data mask / output disable mask 2. dqm truth table h h x n - 1 n / cs h l x upper byte write enable / output enable bsth read read h h x l l x read with auto pre - charge reada write writ h h x l l x write with auto pre - charge writa bank activate act h h x l l x pre - charge select bank pre h l x pre - charge all banks pall mode register set mrs h h x l l x note : h = high level, l = low level, x = high or low level (don't car e), v = valid data input command symbol cke activating any 3. cke truth table h l l n - 1 n / cs x x l / ras x x / cas x x / we x x addr . x x clock suspend idle ref l h h x l h x l x l x h x x idle self self refresh h l l l l h l h l h h h x x idle power down h l l x x h x x x x x x x x remark h = high level, l = low level, x = high or low level (don't care ) command clock suspend mode entry clock suspend mode clock suspend mode exit cbr refresh command self refresh entry self refresh exit power down entry power down exit l h h x x x x
preliminary 11 64 mb sdram ascend semiconductor corporation current state addr . idle x x 4. operative command table action nop or power down nop or power down notes 2 2 ba/ca/a10 ba/ca/a10 illegal illegal 3 3 ba/ra row activating ba, a10 x nop refresh or self refresh 4 remark h = high level, l = low level, x = high or low level (don't care ) / cs h l / r x h / c x h / w x x l l h h l l h l l l h h l l l l h l l h command desl nop or bst read/reada writ/writa act pre/pall ref/self op - code mode register accessing l l l l mrs row active x x nop nop ba/ca/a10 ba/ca/a10 begin read : determine ap begin write : determine ap 5 5 ba/ra illegal 3 ba, a10 x precharge illegal 6 4 h l x h x h x x l l h h l l h l l l h h l l l l h l l h desl nop or bst read/reada writ/writa act pre/pall ref/self op - code illegal l l l l mrs read x x continue burst to end ? row active continue burst to end ? row active x ba/ca/a10 burst stop ? row active terminate burst, new read : determine ap 7 ba/ca/a10 terminate burst, start write : determine ap 7, 8 ba/ra ba/a10 illegal terminate burst, pre - charging 3 4 h l x h x h x h l l h h h l l h l l l l l l l l h h h l desl nop bst read/reada writ/writa act pre/pall x illegal l l l h ref/self write x x continue burst to end ? write recovering continue burst to end ? write recovering x ba/ca/a10 burst stop ? row active terminate burst, start read : determine ap 7, 8 7,8 ba/ca/a10 terminate burst, new write : determine ap 7 7 ba/ra ba/a10 illegal terminate burst, pre - charging 3 9 h l x h x h x h l l h h h l l h l l l l l l l l h h h l desl nop bst read/reada writ/writa act pre/pall x illegal l l l h ref/self op - code illegal l l l l mrs op - code illegal l l l l mrs
preliminary 12 64 mb sdram ascend semiconductor corporation current state addr . read with ap x x action continue burst to end ? precharging continue burst to end ? precharging notes x ba/ca/a10 illegal illegal 3 ba/ra illegal 3 ba, a10 x illegal illegal 3 remark h = high level, l = low level, x = high or low level (don't care ), ap = auto precharge / cs h l / r x h / c x h / w x h l l h h h l l h l l h h l l l l h l l h command desl nop bst read/reada act pre/pall ref/self op - code illegal l l l l mrs ba/ca/a10 illegal 3 l h l l writ/writa write with ap x x burst to end ? write recovering with auto precharge continue burst to end ? write recovering with auto precharge x ba/ca/a10 illegal illegal 3 ba/ra illegal 3 ba, a10 x illegal illegal 3 h l x h x h x h l l h h h l l h l l h h l l l l h l l h desl nop bst read/reada act pre/pall ref/self op - code illegal l l l l mrs ba/ca/a10 illegal 3 l h l l writ/writa precharging x x nop ? enter idle after t rp nop ? enter idle after t rp x ba/ca/a10 illegal illegal 3 ba/ra illegal 3 ba, a10 x nop ? enter idle after t rp illegal h l x h x h x h l l h h h l l h l l h h l l l l h l l h desl nop bst read/reada act pre/pall ref/self op - code illegal l l l l mrs ba/ca/a10 illegal 3 l h l l writ/writa row activating x x nop ? enter idle after t rcd nop ? enter idle after t rcd x ba/ca/a10 illegal illegal 3 ba/ra illegal 3,10 ba, a10 x illegal illegal 3 h l x h x h x h l l h h h l l h l l h h l l l l h l l h desl nop bst read/reada act pre/pall ref/self op - code illegal l l l l mrs ba/ca/a10 illegal 3 l h l l writ/writa
preliminary 13 64 mb sdram ascend semiconductor corporation current state addr . write recovering x x action nop ? enter row active after t dpl nop ? enter row active after t dpl notes x ba/ca/a10 nop ? enter row active after t dpl start read, determine ap ba/ra illegal 3 ba, a10 x illegal illegal 3 remark h = high level, l = low level, x = high or low level (don't care ), ap = auto precharge / cs h l / r x h / c x h / w x h l l h h h l l h l l h h l l l l h l l h command desl nop bst read/reada act pre/pall ref/self op - code illegal l l l l mrs ba/ca/a10 new write, determine ap 8 l h l l writ/writa write recovering with ap x x nop ? enter precharge after t dpl nop ? enter precharge after t dpl x ba/ca/a10 nop ? enter precharge after t dpl illegal 3,8 ba/ra illegal 3 ba, a10 x illegal illegal h l x h x h x h l l h h h l l h l l h h l l l l h l l h desl nop bst read/reada act pre/pall ref/self op - code illegal l l l l mrs ba/ca/a10 illegal 3 l h l l writ/writa refreshing x x nop ? enter idle after t rc nop ? enter idle after t rc x x illegal illegal h l x h x h x x l l h l l h x x desl nop/ bst read/writ act/pre/pall x illegal l l l x ref/self/mrs mode register accessing x x nop nop x x illegal illegal h l x h x h x h l l h h h l l x desl nop bst read/writ x illegal l l x x act/pre/pall/ ref/self/mrs notes 1. all entries assume that cke was active (high level) during the p receding clock cycle. 2. if all banks are idle, and cke is inactive (low level), sdram wi ll enter power down mode. all input buffers except cke will be disabled. 3. illegal to bank in specified states; ? function may be legal in the bank indicated by bank address (ba ), depending on the state of that bank. 4. if all banks are idle, and cke is inactive (low level), sdram wi ll enter self refresh mode. all input buffers except cke will be disabled. 5. illegal if t rcd is not satisfied. 6. illegal if t ras is not satisfied. 7. must satisfy burst interrupt condition. 8. must satisfy bus contention, bus turn around, and/or write recov ery requirements. 9. must mask preceding data which don't satisfy t dpl . 10. illegal if t rrd is not satisfied.
preliminary 14 64 mb sdram ascend semiconductor corporation current state addr . self refresh x x 5. command truth table for cke action invalid, clk (n ? 1) would exit self refresh self refresh recovery notes x x self refresh recovery illegal x illegal x maintain self refresh remark : h = high level, l = low level, x = high or low level (don't care ) / cs x h / r x x / c x x / w x x l l h h h l x x l l x x x x x x self refresh recovery x x idle after t rc idle after t rc x x illegal illegal x illegal x x illegal illegal h l x h x h x x l l h l l x x x h x x x l l h h h l x x x illegal l l x x both banks idle refer to operations in operative command table refer to operations in operative command table refer to operations in operative command table x refresh op - code refer to operations in operative command table refer to operations in operative command table h l x h x x x x l l h x l l l h l h l x l x l x refer to operations in operative command table l h x x refer to operations in operative command table l l h x n - 1 h l l l l l h h h h h h h h h h h h h h h h n x h h h h l h h h h l l l l h h h h h l l l cke power down x x invalid, clk(n - 1) would exit power down exit power down ? idle x maintain power down mode x x x x x x x x x x x x h l l x h l x self refresh 1 l l l h op - code refer t o operations in operative command table l l l l x power down 1 x x x x h h l l l x row active x refer to operations in operative command table x x x x h x x power down 1 x x x x l x any state other than listed above x refer to operations in operative command table begin clock suspend next cycle 2 x exit clock suspend next cycle x maintain clock suspend x x x x x x x x x x x x x x x x h h l l h l h l notes 1. self refresh can be entered only from the both banks idle state. power down can be entered only from both banks id le or row active state. 2. must be legal command as defined in operative command table.
preliminary 15 64 mb sdram ascend semiconductor corporation absolute maximum ratings symbol item rating units v in , v out input, output voltage - 0.3 ~ 4.6 v v dd , v ddq power supply voltage - 0.3 ~ 4.6 v t stg storage temperature - 55 ~ 150 c p d power dissipation 1 w i os short circuit current 50 ma recommended dc operation conditions ( all operating range ) symbol parameter min. units v dd power supply voltage 3.0 v v ddq power supply voltage (for i/o buffer) 3.0 v v ih input logic high voltage 2.0 v v il input logic low voltage - 0.3 v note : caution exposing the device to stress above those listed in ab solute maximum ratings could cause permanent damage. the device is not meant to be oper ated under conditions outside the limits described in the operational section of this specifi cation. exposure to absolute maximum rating conditions for extended periods may affect de vice reliability. typical 3.3 3.3 max. 3.6 3.6 v dd +0.3 0.8 note : 1. all voltage referred to v ss . 2. v ih (max) = 5.6v for pulse width 3ns 3. v il (min) = - 2.0v for pulse width 3ns capacitance ( vcc =3.3v, f = 1mhz, ta = 25 c ) symbol parameter min. units c clk clock capacitance 2.5 pf c i input capacitance for clk, cke, address, /cs, /ras, /cas, /we, dqml,dqmu 2.5 pf max. 4.0 5.0 c o input/output capacitance 4.0 pf 6.5 operating range range ambient temperature vcc commercial 0 ?? c to +70 ?? c 3 v ~ 3.6v industrial - 40 ?? c to +85 ?? c 3 v ~ 3.6v special 0 ?? c to +85 ?? c 3 v ~ 3.6v
preliminary 16 64 mb sdram ascend semiconductor corporation recommended dc operating conditions ( vdd = 3.3v +/ - 0.3 v, all operating range) note : 1. icc1 depends on output loading and cycle rates. specified values are obtained with the output o pen. input signals are changed only one time during tck (min) 2. icc4 depends on output loading and cycle rates. specified values are obtained with the output o pen. input signals are changed only one time during tck (min) 3. input signals are changed only one time during tck (min) 4. standard power version. 5. low power version. operating current parameter test condition burst length = 1, t rc 3 t rc (min), iol = 0 ma , one bank active symbol i cc1 cl=1 precharge standby current in power down mode precharge standby current in non - power down mode active standby current in non - power down mode (4 bank activated) active standby current in power down mode cke 3 v ih (min), t ck = 15ns, / cs 3 v ih (min) input signals are changed one time during 30ns cke 3 v ih (min), t ck = input signals are stable i cc3n i cc3ns cke v il (max.), t ck = cke v il (max.), t ck = 15 ns i cc2p i cc2ps cke 3 v ih (min.), t ck = 15 ns, /cs 3 v ih (min.)input signals are changed one time during 30ns cke 3 v ih (min.), t ck = input signals are stable i cc2n i cc2ns cke v il (max), t ck = 15ns cke v il (max), t ck = i cc3p i cc3ps standard standard low power low power ua ua units ma notes 1 ma ma ma ma ma 2 ma ma ua ua ma m a 3 4 5 u a 1000 500 50 40 35 25 8 8 1000 500 operating current (burst mode) t ccd = 2clks , i ol = 0 ma i cc4 cl=1 self refresh current cke 0.2v i cc6 standard low power 1 500 max - 5.5 - 6 - 7 - 8 - 10 - 15 cl=2 cl=3 -- -- -- -- -- 75 -- -- -- 100 95 -- 135 120 110 100 95 -- cl=2 cl=3 -- -- -- -- -- 80 -- -- -- 110 100 -- 150 140 130 120 110 -- refresh current t rc 3 t rc (min.) i cc5 160 150 145 140 130 85
preliminary 17 64 mb sdram ascend semiconductor corporation ac operating test conditions ( vdd = 3.3v +/ - 0.3 v, all operating range ) output reference level 1.4 v / 1.4v output load see diagram as below input signal level 2.4 v / 0.4v transition time of input signals 2 ns input reference level 1.4 v z = 50 w 50 pf 50 w v tt = 1.4v output parameter test condition symbol max. unit min. input leakage current 0 v i v dd q, v ddq =v dd all other pins not under test=0 v i il +0.5 ua - 0.5 output leakage current 0 v o v dd q, dout is disabled i ol +0.5 ua - 0.5 high level output voltage io = - 4ma v oh v 2.4 low level output voltage io = +4ma v ol v 0.4 recommended dc operating conditions ( continued )
preliminary 18 64 mb sdram ascend semiconductor corporation units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns clk clk clk clk clk ms operating ac characteristics ( v dd = 3.3v +/ - 0.3 v, all operating range ) notes 2 5 5 5 5 5 parameter clock cycle time access time from clk data - out hold time data - out to high impedance time clk high level width clk low level width input setup time input hold time active to active command period active to precharge command period precharge to active command period active to read/write delay time active(one) to active(another) command read/write command to read/write command cl = 3 cl = 2 cl = 3 cl = 2 cl = 2 cl = 3 cl = 2 data - in to precharge command data - out to high impedance from precharge command data - in to burst stop command refresh time(4,096 cycle) cl = 3 cl = 2 data - out to low impedance time symbol t ck t ac t ch t cl t oh t hz t lz t is t ih t rc t ras t rp t rcd t rrd t ccd t dpl t bdl t roh t ref - 6 min. max. 2.5 2.5 2.5 5 1 1 1.5 60 42 18 100 k 18 12 1 6 5.5 2 1 3 2 64 - 7 min. max. 3 3 1.5 5.5 1 1 2 63 18 100 k 18 14 1 7 2.5 45 5.5 2 1 3 2 64 - 8 min. max. 3 3 2.5 1.5 6 6 1 1 2 64 46 18 100 k 18 16 1 8 10 6 6 2 1 3 2 64 - 55 min. max. 2.0 2.0 2.0 4.5 1 1 1.5 60 42 18 100 k 18 10 1 5 .5 4.5 2 1 3 2 64 - 10 min. max. 3 3 2.5 1.5 6 6 1 1 2 70 50 20 100 k 20 18 1 10 10 6 6 2 1 3 2 64 cl = 3 3 4 _ 10 _ 5.5 _ _ 6 6 6 _ _ _ _
preliminary 19 64 mb sdram ascend semiconductor corporation operating ac characteristics -- continues ( v dd = 3.3v +/ - 0.3 v, all operating range ) note : 1. all voltages referenced to vss . 2. for commercial range parts. 3. for industrial range parts. 4. thz defines the time at which the output achieve the open circuit condition and is not referenced to output voltage leve ls. 5. these parameters account for the number of clock cycle and depend on the operating frequency of the clock, as fol lows : the number of clock cycles = specified value of timing/clock period (count fractions as a whole number) 6.these parameters are for address/command/data/clk/cke. 7. any ? ? ? sign on the data means ? no guarantee ? . cl = 1 parameter clock cycle time access time from clk data - out hold time data - out to high impedance time clk high level width clk low level width input setup time input hold time active to active command period active to precharge command period precharge to active command period active to read/write delay time active(one) to active(another) command read/write command to read/write command cl = 1 cl = 1 cl = 1 data - in to precharge command data - out to high impedance from precharge command data - in to burst stop command refresh time(4,096 cycle) cl = 1 data - out to low impedance time symbol t ck t ac t ch t cl t oh t hz t lz t is t ih t rc t ras t rp t rcd t rrd t ccd t dpl t bdl t roh t ref - 15 min. max. 3 3 2 6 1 1 2 90 60 22 100 k 25 15 1 15 1 1 1 64 12 units ns ns ns ns ns ns ns ns ns ns ns ns ns ns clk clk clk clk ms notes 5 5 5 5 5 3 4 6 6
preliminary 20 64 mb sdram ascend semiconductor corporation * ascend reserves the right to change products or specification wi thout notice. package dimension 11.76 +/ - 0.20 0.463 +/ - 0.008 max 0.10 0.004 0.05 0.002 min 0.21 +/ - 0.05 0.008 +/ - 0.002 1.00 +/ - 0.10 0.039 +/ - 0.004 1.20 0.047 max 0.71 0.028 0.35 +0.1 / - 0.1 0.014 +0.004 / - 0.004 0.80 0.035 22.62 0.891 max 22.22 +/ - 0.10 0.875 +/ - 0.004 0 ? 8 ? 0.25 0.010 typ 10.16 0.400 0.50 0.020 0.45 ~ 0.75 0.018 ~ 0.030 0.125 +0.075 / - 0.035 0.005 +0.003 / - 0.001 #1 #27 #54 #28 dimension in milimeter / inchs

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